19 Commits

Author	SHA1	Message	Date
Hong Zhang	7bc5611fb8	ltx2.3 bugfix & ic lora (#1336) ... * ltx2.3 ic lora inference&train * temp commit * fix first frame train-inference consistency * minor fix	2026-03-09 16:33:19 +08:00
Artiprocher	13eff18e7d	remove unnecessary params in cache	2026-03-09 14:09:30 +08:00
mi804	d40efe897f	ltx2.3 train	2026-03-06 18:08:42 +08:00
mi804	ed9e4374af	ltx2.3 docs	2026-03-06 16:45:12 +08:00
mi804	73b13f4c86	support ltx2.3 inference	2026-03-06 16:07:17 +08:00
mi804	1a380a6b62	minor fix	2026-02-28 11:09:10 +08:00
mi804	8b9a094c1b	ltx iclora train	2026-02-27 18:43:53 +08:00
mi804	5996c2b068	support inference	2026-02-27 16:48:16 +08:00
mi804	a18966c300	support ltx2 gradient_checkpointing	2026-02-26 19:19:59 +08:00
mi804	f48662e863	update docs	2026-02-26 11:10:00 +08:00
mi804	8d8bfc7f54	minor fix	2026-02-25 19:04:10 +08:00
mi804	8e15dcd289	support ltx2 train -2	2026-02-25 18:06:02 +08:00
mi804	586ac9d8a6	support ltx-2 training	2026-02-25 17:19:57 +08:00
mi804	2f22e598b7	fix load lora	2026-02-10 15:06:04 +08:00
mi804	b6e39c97af	add inference script for ltx-2 lora	2026-02-10 14:32:30 +08:00
mi804	f4f991d409	support ltx-2 t2v and i2v	2026-02-02 19:53:07 +08:00
mi804	9f07d65ebb	support ltx2 distilled pipeline	2026-01-30 17:40:30 +08:00
mi804	4f23caa55f	support ltx2 two stage pipeline & vram	2026-01-30 16:55:40 +08:00
mi804	b1a2782ad7	support ltx2 one-stage pipeline	2026-01-29 16:30:15 +08:00