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theluyuan
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DiffSynth-Studio
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29bf66cdc926c32164ed1ce8a70bbbe24502582f
DiffSynth-Studio
/
diffsynth
/
utils
History
mi804
a80fb84220
style
2026-04-23 17:31:34 +08:00
..
controlnet
[NPU]:Replace 'cuda' in the project with abstract interfaces
2026-01-15 20:33:01 +08:00
data
acestep t2m
2026-04-21 13:16:15 +08:00
lora
Fix LoRA compatibility issues. (
#1320
)
2026-03-03 11:08:31 +08:00
ses
Merge pull request
#1330
from modelscope/ses-doc
2026-03-06 14:25:45 +08:00
state_dict_converters
style
2026-04-23 17:31:34 +08:00
xfuser
[feat] add VACE sequence parallel (
#1345
)
2026-03-23 15:46:27 +08:00