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https://github.com/modelscope/DiffSynth-Studio.git
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update flux
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@@ -105,6 +105,8 @@ class FluxImagePipeline(BasePipeline):
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self.lora_loader = FluxLoRALoader
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def enable_lora_merger(self):
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if not (hasattr(self.dit, "vram_management_enabled") and getattr(self.dit, "vram_management_enabled")):
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raise ValueError("DiT VRAM management is not enabled.")
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if self.lora_patcher is not None:
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for name, module in self.dit.named_modules():
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if isinstance(module, AutoWrappedLinear):
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@@ -141,7 +143,9 @@ class FluxImagePipeline(BasePipeline):
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pipe.tokenizer_2 = T5TokenizerFast.from_pretrained(tokenizer_2_config.path)
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value_controllers = model_pool.fetch_model("flux_value_controller")
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if value_controllers is not None: pipe.value_controller = MultiValueEncoder(value_controllers)
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if value_controllers is not None:
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pipe.value_controller = MultiValueEncoder(value_controllers)
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pipe.value_controller.vram_management_enabled = pipe.value_controller.encoders[0].vram_management_enabled
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controlnets = model_pool.fetch_model("flux_controlnet")
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if controlnets is not None: pipe.controlnet = MultiControlNet(controlnets)
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pipe.ipadapter = model_pool.fetch_model("flux_ipadapter")
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